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Jeremy F. Burn - IEEE Xplore Author Profile

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3D Heterogeneous Integration (3DHI) of copackaged optics (CPO) emerges as a promising low-power, lowlatency, and high-bandwidth IO solution for the ever-growing datacenter, AI and IoT applications. However, the design and co-optimization of heterogeneous integration of electrical and photonics system is very challenging by multiscale modeling and multiphysics integrity concerns. In this work, a no...Show More
Generally, the tolerance of cryptographic modules implemented in application-specific ICs (ASICs) to side-channel (SC) attacks is evaluated after the silicon manufacturing stage. This post-silicon assessment presents two significant challenges. First, manufacturing ASIC chips is both costly and time-consuming. Second, while post-silicon evaluation can determine the effectiveness of countermeasures...Show More
Integrated circuit (IC) chips equipped with crypto circuits are susceptible to side-channel (SC) attacks that exploit SC information derived from the operation of the crypto circuit to reveal the secret keys. In this paper, we focus on the Si substrate voltage on the backside of the IC chip. The use of flip-chip implementations has led to the emergence of a new threat: direct probing attacks on th...Show More
A large on-chip peak temperature and thermal gradient, caused by localized hotspots and cross-die thermal coupling, can severely impact transistor performance, stress, aging, electromigration (EM), voltage drops, and timing. Generating static and transient chip thermal profiles with traditional FEM/CFD methods have prohibitively expensive computational requirements, especially for three-dimensiona...Show More
Near-field electromagnetic fault injection (EMFI) is one of the most commonly used attack methods to intentionally cause errors in digital circuits due to its inherent advantages. A full-wave simulator was used to analyze the voltage fluctuations on the on-chip power mesh excited by EMFI. We have described the relationship in which the shape of the voltage fluctuations on the power mesh inside ICs...Show More
We introduce four principal contributions to augment the capabilities of Large Language Models (LLMs) in generating domain-specific code: (i) leveraging LLM-based data splitting and data renovation techniques to refine the semantic representation within the embedding space; (ii) proposing an effective method for refactoring existing scripts, enabling the generation of new and high-quality scripts ...Show More
Thermal issues during testing of Very Large Scale Integration (VLSI) chips have become more severe as design complexity increases. Test frequency optimization is needed because high test frequencies can cause thermal damage to circuits under test (CUT), while low test frequencies can result in long test time. In this paper, we propose three techniques to minimize the test time of ATPG scan tests w...Show More
The emerging 3D-IC systems, enabled by advanced packaging techniques, promise high integration density and manufacturing yield to keep Moore's Law thriving. However, due to the complexity of heterogeneous integration of various chiplets into the chip-package-system, applications built upon 3D-IC are challenged by power integrity, signal integrity, thermal integrity, and structural integrity issues...Show More
Optical side-channel analysis poses a significant threat to the security of integrated circuits (ICs) by enabling the disclosure of secret data, such as encryption keys. In this paper, for the first time, we present a multiphysics simulation framework of optical side-channel analysis from the layout database of a fabricated testchip. By leveraging accurate device models and electro-photonic physic...Show More
Soldering and Cu/Cu direct bonding are the two main interconnection approaches in 2.5D/3D ICs advance packaging. The manufacture process of these joints determines the joint quality and has impacts on chip/device performance and reliability. For soldering, this paper proposed a multiscale framework to introduce the influence of solder ball reflow process to further shock reliability simulation. Fo...Show More
High test power causes thermal damage to chips under test. We need power and thermal analyses to ensure thermal safety of ATPG patterns. This requires long runtime and large disk storage because there are many cycles in ATPG patterns. In this paper, we propose power and thermal predictions for test applications. To save runtime, we use multiple ML models and decay surface models for power and ther...Show More
Static chip thermal analysis provides detailed and accurate thermal profile on chip. The chip power map, commonly modeled as rectangular regions of distinct heat sources, significantly impacts the chip thermal profile. Since the heat sources result from numerous cells in functional blocks, the design space of chip power map is prohibitively enormous. Numerical simulations can be reliable for solvi...Show More
Machine Learning technology has been extensively used across engineering simulations, especially for Semiconductor and Electronics applications. Ansys provides an open and extendable framework through PyAnsys on all tools to facilitate customers building customized ML applications. Furthermore, optiSLang, an Auto-ML optimization tool, can be used not only with Ansys multiphysics tools but also wit...Show More
Thermal analysis provides deeper insights into electronic chips’ behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or CFD. Therefore, there is an urgent need for speeding up the on-chip thermal solution to address various system scenarios. In this paper, we propose ...Show More
Trusted microelectronics are increasingly threatened by fault injection attacks through a variety of physical means. Electromagnetic fault injection (EMFI) is a low-cost but effective approach to induce parasitic currents on a victim chip. To address the gap between logic fault principle and silicon EMFI mechanism, a layout-level simulation methodology to identify physical vulnerabilities of the v...Show More
Laser fault injection (LFI) is a formidable physical attack due to its tremendous efficacy, high controllability, and precision. As a result, efforts to simulate laser effects have been undertaken in the literature to study its impact on digital designs. However, most of these efforts either model laser effects on standalone standard cells without considering the impact of layout parameters or pro...Show More
Limitations in traditional methods of thermal analysis call for novel methods to meet emerging needs for chip thermal simulation. The goal in this work is to describe a method to perform transient thermal simulations on chips in multi-chip systems and 3DIC packages, while accomplishing the following key objectives: (1) Capture on-chip hot spots with fine-grain resolution (2) Account for system-lev...Show More
IR-drop becomes an important issue for testing in advanced technology nodes. In this paper, we propose a low-IR-drop test pattern regeneration to produce IR-drop-safe patterns. To speed up IR-drop analysis, we apply an existing machine learning model to predict IR-drop of test patterns. Because we already know the IR-drop of test patterns, we learn from test patterns to determine low-IR-drop prefe...Show More
Large 3DIC designs with multiple chips require several iterations of transient thermal analysis particularly for fine-grain on-chip dynamic thermal management. This requires a fast thermal analysis technology as opposed to traditional CFD/FEA based methods which have severe runtime/capacity limitations for large chips (e.g., 2cmx2cm) in 3DIC while generating fine grained (e.g., 10umx10um) transien...Show More
Vector-based dynamic IR-drop analysis of the entire vector set is infeasible due to long runtime. In this paper, we use machine learning to perform vector-based IR drop prediction for all logic cells in the circuit. We extract important features, such as toggle counts and arrival time, directly from the logic simulation waveform so that we can perform vector-based IR-drop prediction quickly. We al...Show More
The silicon substrate backside of modern ICs is increasingly recognized as a critical hardware vulnerability, which opens a backdoor for laser/optical probing, fault injection and side-channel attacks. In this work, a novel multiphysics simulation framework is proposed to assess near-field electromagnetic (EM) side-channel leakage. By modeling cell-level power, chip logic functionality and layout ...Show More
Accurate side-channel attacks can non-invasively or semi-invasively extract secure information from hardware devices using "side- channel" measurements. The thermal profile of an IC is one class of side channel that can be used to exploit the security weaknesses in a design. Measurement of junction temperature from an on-chip thermal sensor or top metal layer temperature using an infrared thermal ...Show More
Side-channel attacks can non-invasively extract secret information from hardware devices with a large number of “side-channel” measurements. For example, measuring the dynamic voltage drop of a cryptographic chip can disclose the secret keys by power-noise side-channel emission. To identify the design vulnerabilities and to verify the design countermeasures against side-channel attacks, design tim...Show More
This paper describes Reinforcement Learning (RL) based technique for estimating the parameters of ESD generators modeled using circuit templates, given the current discharge waveform. The proposed algorithms can be applied to any circuit template to tune the circuit parameters for the desired application or optimization efficiently with minimum prior knowledge. The model can then be used in system...Show More
Accurate prediction of on-chip temperature distribution becomes important for the performance and reliability of upcoming 5G, automotive, and AI chip-package-systems. In particular, a large thermal gradient (the temperature variation across a chip) accelerates electromigration and aging, and also impacts design performance and power. Furthermore, there are usually Tmax (maximum temperature) constr...Show More