Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage $(V_{\mathrm{ th}})$ of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( $t$ ). A device-level approach for $V_{\mathrm{ th}}$ degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of $t$ . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with $t$ to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.