Speed and Power Tradeoff Based on FinFET Structure, Voltage Changing and Circuit Layout

In order to achieve IC requirements of larger scale, higher speed and lower power consumption, various short channel effects, drain-induced barrier lowering and other problems faced by traditional CMOS devices while channel shortening has been becoming more and more serious. The literature mainly classifies, sorts out and summarizes the classical methods and research status based on speed-power tradeoff of FinFET. In terms of self-structure feature and additional factors, it separates approaches into FinFET optimization, voltage change and circuit layout design. Representative instances of each type are analyzed, classified and encapsulated in detail from their advantages and disadvantages. The contribution of each type to the tradeoff is also systematically expounded. Finally, the possible future research directions and corresponding development trends in this field are predicted and described.