FPGA-Based Implementation of I/Q Chirp Signal Generator Using Memory-Based Technique

In this study, we evaluated the I/Q chirp signal generator using a field-programmable gate array (FPGA) to be implemented for synthetic aperture radar (SAR) application. A chirp signal is a sinusoidal signal with a constant amplitude that, over a brief period of time, either increases in frequency from low to high (up-chirp) or decreases in frequency from high to low (down-chirp). To simplify our proposed design, a memory-based technique is employed to store the generated output chirp signal where the in-phase (I) and quadrature (Q) signals are stored in a rom-based look-up table separately. To reduce circuit usage, a single accumulator that points to the address of both look-up tables is leveraged to generate the I/Q chirp signal through dual-channel DAC chips. From the experimental results, by using an Altera Cyclone IV FPGA, we demonstrated the capability of the system to generate the I/Q chirp signal at 10 MHz of bandwidth for a period of 10 μs.