Reconfigurable Cyber-Security Architecture for Small Satellite with Low Complexity and Power

Small satellites are extensively developed to serve a wide range of space missions, from exploration to defense. They are becoming a promising replacement for large spacecraft due to their low development cost and lead time. Small satellites are widespread in the Low Earth Orbit (LEO), and they are operated by governments, space agencies, universities, and companies. The communication between satellites and ground segments is vulnerable to different cyberattacks where attackers can access critical data that could jeopardize national security. Thus, satellite communication cybersecurity has become a crucial role in the sustainability of satellite systems, where some of these vulnerabilities can negatively impact the mission. The design of small satellites has many challenges such as low power consumption, limited data rate, and limited design area. This research paper proposes a revised onboard cybersecurity architecture for small satellites. A hardware implementation of an optimized Advanced Encryption Standard (AES) algorithm was implemented to optimize the design complexity and power consumption. The optimized AES algorithm was implemented using a reconfigurable Field Programmable Gate Arrays (FPGA) device Spartan-6 to evaluate the performance, resource utilization, and power consumption compared to existing Commercial off-the-shelf components (COTS). The results show high performance for securing data and images with low power consumption and low complexity, making it suitable for small satellites.