Hardware Implementation of Address Register Circuit on VLSI Based FPGA Device

In this study, we construct an (AR) address register that is responsive to voltage increases. We investigated the power dissipation of an address register using the Xilinx 14.1 ISE tool, and the address register code is written in the Verilog hardware description language. In this research, we employed two FPGAs, one Virtex 4 and one Virtex 5, to investigate the power consumption of AR. We measured the difference in on-chip power required by AR by increasing the voltage from 1.0 V to 2.0 V. We discovered that lowering the voltage reduces power usage. Power consumption is greater for both FPGAs at 2.0 V. Therefore, to initiate the idea of Green Communication (GC) AR should be best suited with Virtex 4 FPGA.