Design of serial-parallel converter based on FPGA

In this paper, the design of an 8-bit serial-parallel conversion system which can be applied to FPGA is presented. Serial-parallel conversion is a very common design and be widely used in digital electronic systems. In communication systems, using parallel data bytes and transmitting them over a single line can be efficient in saving wire area, reducing crosstalk effects, increasing clock speeds, or maintaining compatibility between devices. However, with the upgrading of the processing speed and frequency of FPGA, the serial-parallel conversion using the basic chip seems to be no longer reliable. Therefore, based on the existing problems, in this paper, the development and simulation process of a PFGA-based serial-parallel conversion system is introduced. The system consists of a 4-bit counter module, Series/parallel conversion module, which is composed of multiplexers and flip-flops, combination module. The counter is used to control the time of the overall system and provide the function of reset. The series/parallel conversion module convert an 8-bit parallel signal to a serial signal firstly, after the transmission and processing, it is restored to the original parallel signal again. The combination module makes the whole system work orderly. The system is implemented with VHDL language. The rationality of the system is verified by experiments.