PCIe device drivers in Linux : Design and implementation of a high-speed PCI Express bridge

In this design we will implement a bridge that enables communication with hardware that does not have native PCI Express support. The bridge should convert PCI Express to Low Voltage Differential Signaling (LVDS) and/or CMOS-logic. LVDS and CMOS covers the most frequently used solutions for communicating between different hardware; differential and single-ended. Furthermore, the (CMOS/LVDS) side should be easily reconfigurable in order to support different types, amounts and combinations of interfaces. The design should be able to interface with at least a PCI Express Gen1 x2 interface, meaning that there are two data lanes at 2.5 GT/s. Later generations are desirable but not necessary. The lane configuration (x2) must not change. The design should act as a PCI Express endpoint. The interface should be able to support both LVDS and CMOS interfaces. The number of interfaces should be configurable to suit the application. Furthermore, each interface should be able to transmit data at up to 150 MHz ^[10].