Estimation of power consumption in encoded data buses

Because of the increasing importance of cross coupled capacitances in deep submicron technologies, it is of great interest to extend the existing high-level power estimation techniques by considering the spatial correlation between adjacent lines. This work addresses the modeling and estimation of power dissipation in on-chip buses based on the statistical properties of data sequences. Using the derived models, a power estimation technique is proposed and evaluated for various coding schemes. For different DSP applications, our results depict less than 5% discrepancy with precise bit level estimations.