Power and Area Efficient Charge-Pump Design for PLL Application

As the design of charge-pump (CP) circuits has progressed, some notable non-idealities, such as current mismatch, phase noise, and reference spur, have been noticed. One of the most important aspects of an effective CP design is lock-in time, yet achieving it always presents a challenge for usage in high-speed mobile communication. This work describes a straightforward drain switching-based charge-pump that uses minimal electricity. There is just an estimated 42.60 µm
²
of layout area. The suggested circuit is modelled using the CADENCE VIRTUOSO platform with 90nm CMOS technology working at 1.25GHz at 1.2V supply voltage. In comparison to the preconfigured circuits, the phase noise is stated to be -99.43 dBc/Hz @10MHz, and the current-mismatch is estimated to be 0.73% with an output range of 0-0.85V and lock-in time of 26ns. This qualifies it for PLL applications. To verify the effectiveness of a novel charge-pump circuit, Monte Carlo and process corner analysis are used.