A 217.8 MSOPs/W FPGA-based Online Learning SNN Processor Using Unified Event-Driven Structure and Topology Aware Data Reuse Strategies

The high power consumption caused by machine learning-related intensive computing has become a concern of global researchers. In recent years, neuromorphic hardware and algorithms are attracting more and more attention due to the low power consumption and high plasticity of spiking neural networks (SNN) [1–6]. However, this novel type of neural network raises new challenges from a hardware perspective shown in Fig. 1. 1) The information in the SNN is processed and transmitted in the form of sparse event pulses. It is difficult for traditional accelerator architectures based on parallel computing to fully exploit unstructured sparsity due to the inconsistent memory access; 2) Time-multiplexed crossbar architecture is broadly used in existing neuromorphic hardware to support different SNN topologies [1], but data reuse and support for different SNN topologies are not fully considered under such architecture. 3) In addition to inference, online learning is an important feature of SNN. Existing works tend to support online learning with separated modules [1,2,4,5], which results in additional resource overhead.