A 65nm 8-bit All-Digital Stochastic-Compute-In-Memory Deep Learning Processor

High compute density improves the data reuse and is the key to reducing off-chip memory access and achieving high energy efficiency in ML accelerators. Compute-in-Memory (CIM) promises high compute density but requires ADCs, DACs that add to the macro’s energy and area [1] [2] limiting its compute density. Besides, CIM’s analog compute is sensitive to process variability and mismatches. The transistor nonlinearity also significantly degrades the compute accuracy. Stochastic Computing (SC), which represents numbers as probability of 1s in random binary streams, is a digital-compute scheme that uses tiny MACs and offers high compute density without ADC/DAC (Fig. 1). Simulations show 4x reduction of memory access compared to 8b fixed-point digital accelerators due to the massive parallelism it can achieve using the tiny digital logic gates (AND/OR). However, SC suffers from high cost of binary to stochastic number conversion and compute error.