Terabytes and Terabits/s Packet Caching in ICN Routers using Programmable Switches

This paper designs a per-packet caching mechanism of information-centric networking (ICN) routers on a combination of a programmable switch and computers, where DRAM devices of the computers are used to cache data packets. The forwarding bottleneck for the routers is the switch ports’ bandwidth consumed by sending data packets between the switch and the computers. In order to resolve the bottleneck, the paper proposes two algorithms to reduce traffic between them: cache admission and lazy responses. The prototype implementation demonstrates the feasibility of Tbps- and terabyte-class caching.