An optimized RISC-V processor with five stage pipelining using Tournament Branch Predictor for efficient performance

A RISC-V is an open-source standard computer architecture that uses reduced instruction sets and provides researchers and developers to learn, develop and contribute to the existing architecture. The computer organization covers a huge range of scope for development. One such scope, is the branching technique in an architecture that contributes to the speed and accuracy of the execution and hence leading to one of the important factors for improving the efficiency of the processor. The methodology and design to implement such different branching techniques and the importance of branch predictors has been a major part of the research. The design of a micro-architecture and implementation on the existing processor has brought up the scope of analyzing and comparing these techniques. A tournament branch predictor has been designed and implemented using previously used branching techniques to increase the processor speed and achieve better accuracy. The comparative analysis of a tournament branch predictor shows greater number of instructions is executed in a tournament branch predictor. Instruction per second (IPS) rate for a branch comparator is 3.93 x 10
^{^9}
whereas for a tournament branch predictor architecture, the rate is 2.18 x 1010 which executes 10 times more instructions per second.