Design and Analysis of 8-Bit Multiplier for Low Power VLSI Applications

Multiplier is the most essential and primitive element of multiply and accumulate (MAC) unit, and is typically found in many digital signal processing (DSP) applications. Conventionally the multiplication operation is carried out through repeated addition; hence multipliers use extensively the full adders (FAs) for the addition process. The energy efficiency of the multiplier is determined in terms of power delay consumed per bit operation. Thus, FA plays a vital role in determining the overall efficiency of the multiplier. In this paper, a study, design, and simulation of an 8-bit additive multiply module (AMM) using different FA circuit architectures is presented. Further, the designed AMM is compared against the traditional Wallace and Dadda tree multipliers in terms of design metrics. To perform comparison of all the multipliers, they are described using RTL codes, simulated and verified using Cadences’ EDA tools. To extract power and area metrics, the verified designs are further synthesized under common constraints using Cadences’ generic 180 nm technology file.