6T SRAM Cell Design Using CMOS at Different Technology nodes

SRAM (Static Random Access Memory) has become a major key component in many VLSI Chips, due to its high storage density and quick access time, it has become a popular data storage device. SRAM has played a significant role in the global VLSI sector. Due to the significant increase of low power and low voltage memory systems in recent times, SRAM has been prioritised in the research sector. This is owing to the increased demand for high-end devices, IC memory cards, and other communication devices, as well as the advancement of portable battery-operated devices. The power and area of a low-power 6T SRAM cell design are assessed in this research. This work describes the design and implementation of a 6T SRAM cell in standard CMOS process technology at 180nm, 90nm and 45nm nodes. In the Cadence Virtuoso Software, this simulation was run. The Static Noise Margin has been used to analyse the performance of SRAM cells. The schematic, transient simulation, and DC analysis are all included in this work.