A Low Power CMOS Analog Multiplier using Regulated Cascode Current Mirror based on Translinear principle

This study discusses a new method for designing four-quadrant CMOS analog multipliers. The suggested multiplier circuit's main core is made up of cascode current mirror, there are two common pairs of translinear loops that form a symmetrical arrangement for the multiplier. As the resultant non linearity's in both squarer circuits is subtracted from each other, this characteristic reduces error. In addition, in comparison to conventional architectures, the multiplier circuit's shared bias branch consumes less power. In other words, instead of two bias branches, both squarer circuits employ a single one. A 623 MHz −3dB bandwidth and 69.55 μW maximum power consumption 24.6% lower than previous work[1], 1.5V is the maximum supplied voltage in 180nm technology.