Time-Mode z-1 Programmable Multiplier

This paper proposes a novel circuit of a
$z^{-1}$
time-mode programmable multiplier with improved accuracy which can be used as a basic building block in time-mode filtering and signal processing. The proposed circuit is based on the time register topology which employs the capacitor discharging approach. The circuit is built using 28
$\boldsymbol{nm}$
Samsung FD-SOI process with
$\boldsymbol{a}$
1
$V$
supply voltage. The sampling frequency is 5
$\boldsymbol{MH_{Z},}$
and the average current consumption is
$\boldsymbol{102\mu A}$
,. The circuit performance is verified through simulations, featuring a linear programmable multiplication coefficient between 0.05 and 1 with a step of 0.01.