Design and Implementation of a High-Performance 4-bit Vedic Multiplier Using a Novel 5-bit Adder in 90nm Technology

A multiplier is an essential component in high-performance systems including digital signal processors, arithmetic & logical units (ALU), and various other communication systems. The multiplication method essentially needs a lot of hardware resources and more computation time than the other arithmetic operations such as addition and subtraction. In recent years, the development of portable electronics has compelled developers to enhance the existing multiplier designs for improved performance. Vedic mathematics consists of five sutras(formulas) for multiplication; however, the Urdhva Tiryagbhyam sutra is principally utilized as it is a general sutra suited for all types of multiplication providing faster computation with minimum delay time. The proposed architecture in this work uses a novel 5-bit special adder along with conventional full adders and half adders for implementing the 4*4 multiplier using the Urdhva Tiryagbhyam technique of Vedic Mathematic. The multiplier modules are designed in the Cadence Virtuoso System design platform. Subsequently, the conventional and proposed 4- bit multiplier designs are simulated and verified in the Cadence spectre simulation platform in a 90nm CMOS technology library file. The results show an overall improvement for the proposed 4*4 Vedic multiplier with a 52.2% reduction in power, 48.6% reduction in delay, and 75% decrease in the power-delay product (PDP) of the circuit against the conventional CMOS Vedic multiplier.