Multi-Constant Multiplication Optimization Based on Common Sub-Expression Elimination

Constant multiplication refers to multiplying an unknown variable with one or more known constants, which has a wide range of applications in the field of digital signal processing and artificial intelligence. How to implement the circuit of constant multiplication with optimized cost and performance is an important problem in logical synthesis research. In this work, we propose a novel multi-constant multiplication optimization algorithm based on common sub-expression elimination. It eliminates the common sub-expression with the most occurrences among the multiple constants in each iteration, so as to share more among the corresponding circuit realizations and lead to better optimization. The experimental results show that the proposed algorithm consumes similar runtime to the built-in algorithm of Design Compiler and achieves 31 × speedup compared to the graph-based heuristic algorithm [1]. At the same time, it brings remarkable area reduction and comparable or better delay on the synthesized circuit than the baselines.