A statistics-based background capacitor mismatch calibration algorithm for SAR ADC

This paper presents a statistics-based background capacitor mismatch calibration algorithm for successive approximation register (SAR) analog-to-digital converter (ADC). The calibration algorithm is capable of detecting capacitor mismatch errors based on statistical principles and signal correlation is eliminated by introducing additional dummy capacitors, leading to fast convergence. This calibration increases the signal-to-noise-and-distortion ratio (SNDR) from 64.57dB to 82.03dB and achieves 29dB spurious-free dynamic range (SFDR) improvement. The simulated differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.17/-0.13LSB and +0.36/-0.38LSB respectively.