Efficient Verilog implementation of Neural Networks for Handwritten Character Recognition

Field Programmable Gate Arrays (FPGAs) have been playing an extremely important role in various industries as it has highly parallel architecture, consumes low power, and is flexible in custom algorithms. For training and implementing the NN (Neural Networks) and also machine learning algorithms, efficiency in terms of power and a parallel architecture is of great help. Instead of having an entire CPU setup ready, a compact FPGA unit consumes less area as well and comes in handy when it comes to compactness. Keeping the importance and benefits of FPGA over a dedicated Computing unit the paper mainly focuses upon the Verilog implementation of Neural Networks for the application in Character recognition system. The system takes inputs from 0 to 9 and tries to detect the character based on the trained neural network. This Neural Network is trained using MNIST dataset in such a way that it should be able to detect the digit from 0–9 with high efficiency.