Distributed PDN Modeling Approach for Accurate Jitter Estimation in High-Speed NAND Flash Memory

Due to aggressive storage capacity demands, multiple NAND Flash die are often stacked in a highly integrated, complex package system. As data-rate increases, bit time (UI) is shrinking, and accurate measurement of the data valid window and jitter become very important. Power distribution network (PDN) noise affects the overall system timing. The conventional way of PDN modeling approach in NAND Flash memory System level analysis, cannot accurately predict the system level jitter and deviates from the actual product level performance. In this paper, an accurate method for PDN-induced jitter analysis in NAND Flash system-level operation is described. Simulated PDN-induced jitter results are validated through characterization system and product level measurement jitter.