Fault Modeling and Testing of RRAM-based Computing-In Memories

Resistive random access memory (RRAM) is one promising nonvolatile memory. It also is a good candidate for realizing computing-in memories. In this paper, we perform fault modeling for 1T1R RRAM-based computing-in memories (CIMs). Although there are existing works reported fault modeling and testing for RRAMs and RRAM-based CIMs, they do the fault analysis based on bit-oriented array organization. Here we inject intra-cell and inter-cell electrical defects in a word-oriented cell array for the fault analysis. Fault analysis results show that a RRAM-based CIM may have computing faults and data dependent faults in addition to conventional RRAM faults. We also propose a march test March-R11N for the 1T1R RRAM-based CIMs. Analysis results show that March-R11N requires 11N test complexity to cover all the typical faults and defined faults of a 1T1R RRAM-based CIM with $N$ words.