Simulation and hardware validation of SerDes links for SpaceFibre

The advancement of complex on-board data-handling networks constitutes a need for high-speed data links. SpaceFibre has been developed with its quality of service (QoS), fault detection, isolation and recovery (FDIR) capabilities and high data rates (up to 6.25 Gbps per lane). In 2019 a common ECSS standard has been published, which describes the basis of the protocol and its physical layer. However, a compliance testing methodology has not been described yet. Thus, this paper intends to provide a set of hardware validation and simulation-based verification strategies for SerDes links that result in best practice design guidelines. The methodologies have been evaluated with simulations and hardware tests of a FPGA-based data processing board, supporting the SpaceFibre standard on both the backplane and the front-panel connectors.