Modeling and Analysis of PBTI, and HCD in Presence of Self-Heating in GAA-SNS NFETs

Ultrafast measurements (10-
$\mu \text{s}$
delay) are done to characterize the time evolution of threshold voltage shift (
$\boldsymbol {\Delta } {V}_{T}$
) due to the positive bias temperature instability (PBTI) and hot carrier degradation (HCD) in gate all around stacked nanosheet (GAA-SNS) N-channel field-effect transistors (NFETs).
$\boldsymbol {\Delta } {V}_{T}$
time kinetics are analyzed at different gate voltages (
${V}_{G}$
) and temperatures (
${T}$
) during PBTI, and at various
${V}_{G}$
/drain voltage (
${V}_{D}$
) during HCD. PBTI contribution during HCD is estimated with a physics-based BTI analysis tool (BAT) framework in presence of self-heating (SH) and nonuniform vertical field (
${E}_{\text {VRT}}$
) covering full
${V}_{G} / {V}_{D}$
span and intrinsic HCD contribution is decoupled.