Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops

We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is apparent that the proposed approach can be practiced for every digital circuit with combinational loops. In regard to hazard detection, a simulation-based semi-modular analysis is presented, by extending the provided library technology behavioral Verilog files. For hazard elimination, only the standard cells within the paths causing a hazard have been included for analysis. The circuit becomes hazard-free by inserting buffers of the minimum required delay. We develop three path-based buffer insertion approaches; the more advanced ones model each logic gate and their relative timing constraints as a maximum set covering problem. The main characteristic of comparison is the count of inserted buffers and their total delay. The aforementioned hazard analysis is an iterative process, because the overall timing constraints of the circuit alter after each delay insertion. Experimental results indicate that the three hazard elimination approaches have various area penalties and their success rate ranges from 68.7% to 100%. Moreover, not all hazards can be resolved, mainly due to opposing constraints of sensitized hazard paths, and Boolean logic re-synthesis may be required.