An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC

This paper presents a fast transient response flipped voltage follower (FVF) low-dropout regulator (LDO) for high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs), enabled by a direct-coupled auxiliary loop (DC-AL) with replica load. The proposed auxiliary loop consists of an additional power MOS directly controlled by a replica load, which imitates the response of the main loop but scaled down for low power and compact area. This low die cost solution enables a fast transient response from the LDO that well suits a high-speed SAR ADC. The concept, verified in a 12bit V
CM
-based SAR ADC in 65nm CMOS, operates at 100 MS/s under a 1.2 V supply. The simulation results demonstrate that the DC-AL scheme improves the worst-case DNL and INL from 2.05/-1 LSB and 1.91/-1.83 LSB to 0.43/-0.46 LSB and 0.56/-0.52 LSB, respectively. The LDO with the DC-AL as the reference buffer consumes 0.65 mW with only 0.5 pF of decoupling capacitance, while the DC-AL spends only 0.08 mW.