Evaluation of Statistical Fault Analysis Using Input Timing Violation of Sequential Circuit on Cryptographic Module Under IEMI

In encryption circuits, the threat of fault injection analysis remains a considerable problem. More specifically, clock glitches generated by intentional electromagnetic (EM) irradiation cause faulty operations and estimate internal secret keys. Generating clock glitches via intentional EM interference (IEMI) can be performed without opening the equipment, which makes it a real threat. Previous secret key analysis via IEMI has focused on setup time violations. It requires the clock glitch to occur near the critical path delay of the encryption circuit. This article examines the faults owing to timing violations of inputs to the sequential circuit and discusses the possibility of obtaining the secret key from the output of the faulty ciphertext. The input timing violation of the sequential circuit covers all times during the operation. The bias of the output value of the sequential circuit owing to input timing violations is evaluated using a measurement system in which the sequential circuit alone was extracted. Secret key analysis of encryption circuits using the bias of output values is performed for three different implementations of the advanced encryption standard to demonstrate its feasibility. The results indicate that secret key analysis is possible over a wide range of shortened clock period, regardless of the implementation method.