Think Nontraditionally for Future ESD Protection (Invited)

It is quite a consensus that ESD Design Overhead, including both ESD-induced parasitic effects (e.g., capacitance, leakage, noise) and layout difficulty (large size and floor planning), is becoming increasingly unacceptable to advanced ICs at smaller technology nodes, from lower power to high-frequency to high-throughput chips. Major efforts have been devoted to craft the ESD-Critical Parameters and minimize the ESD design overhead effects in practical ESD protection designs. Yet, it is still extremely hard to meet the needs of even modest ESD protection robustness for sophisticated ICs these days. Lowering the bar for ESD protection was therefore suggested, which however is not uncontroversial. An alternative possibility to overcome the mounting ESD protection pressure for future chips is to think about ESD protection mechanisms and structures nontraditionally. This paper reviews a few disruptive ESD protection concepts for future ESD protection considerations. The first new concept is a nano crossbar array ESD protection device, the second new concept is a graphene-based NEMS switch structure, both can be built above-IC in CMOS backend, and the third concept is to use graphene nano ribbons for ESD protection interconnects. The new ESD protection mechanisms, device prototypes, encouraging results and design challenges are discussed, aiming to draw R&D attentions and inspire nontraditional thinking.