A Waveform Sampling Prototype ASIC for Picosecond-Level Time Measurement

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction.