A MPW splicing algorithm based on machine learning

With the development of integrated circuit technology, especially after the feature size of integrated circuit has entered the deep submicron stage, the use of many similar technologies, such as optical proximity effect correction (OPC), phase shift mask (PSM) and so on, makes the manufacturing cost of integrated circuits increase sharply. Multi-project wafers (MPW) stream multiple IC designs using the same process on the same wafer, and the IC designs participating in the same multi-project wafer project share the cost of taping according to the area and so on. Most of the existing methods are difficult to represent arbitrary polygon layout, and it is not convenient to design machine learning optimization goals. In this paper, we propose a layout optimization methodology based on machine learning framework to solve the splicing problem of MPW. The polygons are cut into rectangle and represented in Euclidean space, so that the minimum splicing area between chips can be achieved through gradient descent optimization and simulated annealing. The experiment results indicate that the proposed PCB routing method can obtain more than 95% area utilization, while the aspect ratio is approximately 1.