A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS

This paper presents a compact 4x delta-interleaved switched-capacitor (SC) digital-to-analog converter (DAC) for digital-intensive transmitter architectures. To minimize area and leverage the strengths of FinFET technology, the implementation departs from the traditional current steering approach and consists mainly of inverters and sub-femtofarad switched capacitors. The DAC's architecture is based on parallel charge redistribution, and separates level generation, pulse timing and output power generation. The 16 nm FinFET 8-bit prototype occupies only 0.011 mm
²
while running at 56 GS/s and providing up to 0.27 V
pp
signal swing across its differential
$100\ \Omega$
load. It achieves an
$\text{IM3}\leq-48\, dBc$
and an
$\text{SFDR}\geq 42\ \text{dB}$
within its ≈ 10GHz output bandwidth while consuming 280mW from a single 0.85 V supply.