Configurable Universal QC-LDPC Encoder Architecture Design

Quasi-cyclic low-density parity-check (QC-LDPC) codes are widely used owning to its good performance and easy hardware implementation. However, most classical LDPC encoder designs do not support changing the LDPC code types or parameters according to different communication services and channel conditions. In this paper, we propose an encoder architecture with configurable code types, input information block lengths, coding rates and degrees of parallelism, which can realize “hot-switching” of configuration parameters. A new scheme that makes full use of the characteristics of the generation matrix is used in the core of parallel coding. The implementation on field programmable gate array (FPGA) shows that the throughput of the encoder can reach 1.6 Gbps under the condition of 7/8 coding rate (8176, 7154) and the degree of parallelism set to 8.