A Nine-Level Inverter With Single DC-Link and Low-Voltage Capacitors as Stacked Voltage Sources With Capacitor Voltage Control Irrespective of Load Power Factor

This article proposes a multilevel inverter topology with single dc-link and series-connected capacitors as stacked voltage sources for multilevel voltage generation. The voltage deviation of a dc-link capacitor will occur whenever a phase terminal connects to the balanced neutral points (NPs: terminal joints of dc-link capacitors). On the contrary, if the voltage of a dc-link capacitor deviates from the nominal voltage, the same phase currents can be utilized to balance these NPs. This new technique is being proposed for the first time in the literature. Any voltage disturbance of the dc-link capacitors is balanced using the motor phase currents, irrespective of load power factor and modulation indices. For the balanced NPs, whenever a phase connects to an NP, the other phase terminal tapping positions are varied on the dc link to establish $i_{A}+i_{B}+i_{C}=0$ for that NP. The pole voltage level variation at motor phase terminals is undisturbed by adding extra cascaded H-bridges (CHBs) at each phase leg. The voltages of CHB capacitors are controlled conventionally by inverter pole voltage redundancies. The detailed experimental results for open-loop V/f and closed-loop field-oriented control on an induction motor are presented using a nine-level laboratory prototype.