Short circuit faults in state-of-the-art ADCs - are they hard or soft?

For next generation deep sub-micron (DSM) analogue and mixed signal ICs, the integration of Design-for-Test (DfT), Design for-Manufacturability (DfM), Defect-Oriented Test (DOT) approaches, and Built-In Self-Test (BIST) techniques into the design and manufacturing cycle will gain increasing importance to the context of implementing a structural IC test methodology (1). This paper discusses the relevance of fault simulation techniques to investigate realistic circuit failure modes and test requirements. It is shown for an ADC target design that hard faults frequently cause marginal rather than catastrophic failure, hence have to be subject to test.