Thermal Design of a Chiplet Module using Monolithic die and 2.5D/3D packages

In this paper, the thermal performances of a Chiplet module designed with various configurations, such as monolithic die, 2.5D interposer, and 3D stacked dies, were studied and compared. The chiplet module was assumed to be placed in the same server system, with the same ambient condition, and using the same heat sink, to compare the differences of their thermal performances with a simulation. To mitigate the junction temperatures, a vapor chamber was designed inside the heat sink base, and different thermal interface materials and packaging structures were studied. Finally, with the calculation of the thermal resistor matrix, a unique power envelope plot was developed to determine if the power magnitudes of the chips on the chiplet module caused the reliability concern. The power envelope plots are a good tool for designers to optimize the power magnitudes, especially at the early stage of the chiplet module design.