Analysis of Abnormal GIDL Current Degradation Under Hot Carrier Stress in DSOI-MOSFETs

It is generally believed that the gate-induced drain leakage (GIDL) current would increase with the hot carrier stress (HCS) time. As more interface electron traps are generated near the drain side, it results in a steeper energy barrier that makes the band-to-band tunneling (BTBT) process much easier. In this work, however, an abnormal decrease of such leakage current was observed in double silicon on insulator MOSFET under floating body (FB) condition. Through systematic characterization on different devices and operation conditions, we find that this behavior can be explained by the activation of lateral parasitic bipolar transistor (PBT), and the subsequent reduction of its current gain after the stress cycle. This is further supported by the simulation results that the induced additional traps would lower the amplified current by increasing the electron recombination rate. Our findings would shed more light on the roles of interface traps played in the MOSFET reliability analysis.