A 10-to-12-GHz Dual Loop Quadrature Clock Corrector in 28-nm CMOS Technology

This paper presents a 10-to-12-GHz dual loop quadrature clock corrector consisting of quadrature phase error corrector (QEC) and duty-cycle corrector (DCC) using a digital delay-locked loop (DLL). To ensure stability, QEC and DCC loops operate concurrently with different bandwidths. The correctors use a shared phase comparator scheme to minimize the calibration-induced error. The chip is implemented in 28-nm CMOS technology with an active area of 0.016 mm2. The calibration loops consume 16.5 mW at 12 GHz on a 1.0- V supply, with 0.6 ps residual clock phase inaccuracy and 0.7 % duty cycle error.