Enhanced Shifting Method For an Area-Efficient Design of FIR Filter Based on FPGA

The Finite Impulse Response (FIR) filter is an important part of a Digital Signal Processing (DSP) system. The Multiply and Accumulate (MAC) technique is used to compute the FIR filter. Traditional MAC units are slow and require a lot of area when implemented in hardware. This paper presents the design and implementation of a 16-order efficient FIR filter. This work proposes a modified shift and add method to design the FIR filter by replacing the multiplication with only shift registers and add blocks. FIR filter was constructed using the equiripple method in MATLAB R2012a, which was then implemented on Xilinx FPGA Spartan3A and Spartan3AN xc3s700a-4fg484. The results show that the proposed method occupied only 463 slices, and 601 LUTs, which means a 56.52% reduction in No. of slices and 66.29% reduction in LUTs from the traditional transversal form.