Slew Rate Calibration Method for High Speed Systems

The slew rate calibration method for high speed systems is presented. In high-speed systems driver output slew rates variation becomes significant. This variation impact on overall system stability and timing closers. The proposed method calibrates slew rate of output in systems to provide equals rise/fall slew rates to improve performance and avoid functional fails. Slew rate of system changes over process voltage temperature (PVT) and having fixed one slew rate code may cause slew rate mismatch. The slew rate mismatch is critical in many systems such as Double Data Rate (DDR). As DDR signal applies to SDRAM (chip to chip) so slew rate mismatch can cause functional fail after transmission line. The proposed slew rate calibration method also decreases TX jitter. Fixing slew rate mismatch inter-symbol interference (ISI) effect on TX signal decrease which causes low jitter. The proposed architecture can be used in high speed systems where data rates are 4Gbps or higher. Modern high-speed serial links require slew rate calibration and proposed method can be used in special input/output circuits of several standards such as (DDR), Universal Serial Bus (USB) and Peripheral Component Interconnect (PCI).