An Efficient Implementation of Booleans Functions as Quasi Delay Insensitive Combinational Circuits

Digital circuits nowadays are implemented in the MOS nanometer technology and have critical requisite such as energy consumption, performance, hardiness, etc. Such circuits implemented in synchronous style with global clock signal can have design difficulties, such as clock skew, timing analysis, satisfying power demand, etc. Asynchronous style is a promising alternative for clock signal related problems. The class of asynchronous circuits QDI (Quasi Delay Insensitive) is a class with low electromagnetic emission and highly robust to noise and PVT variations (Processes, Supply Voltage and Temperature), being able to work with sub-threshold voltages. This paper presents a simple approach for synthesizing QDI combinatorial circuits, which obtain high area reduction and implement their circuits with basic gates and C elements. When compared to the main methods of the literature, the method presents promising results of up to 46.0% in the reduction of the number of transistors.