Hardware Up-gradation Plugin for Accelerating the Image Convolution Processing

Data collection in the form of Images or videos and its further processing is becoming an inevitable part of many recently developed advanced technology-based devices. For extracting specific and meaningful information from all these large data sets, large computational power is needed. Therefore, the use of heterogeneous system came in to existence in which the existing serial processors are combined with parallel computing processors to produce better output. Most of the applications in image processing have high inherent parallelism. Despite of having low operational frequency FPGAs are capable of generating seemingly high performance by extracting the parallelism to the fullest. In the present manuscript parallel image convolution algorithm is proposed and implemented on FPGA present on Arty Z7 board. The Arty Z7 board can be used as Hardware Up-gradation Plugin (HUP) in hybrid computing systems. The performance of this proposed method is compared with CPU and GPU operating with parallel convolution algorithm. Similarly, it is also compared with serial convolution architecture implemented on FPGA. It is observed that parallel image convolution algorithm consisting of two convolution modules implemented in HUP is producing better results than serial convolution architecture. Further, 8 and 16 parallel convolution modules in HUP performs faster than CPU and GPU for image convolution.