A 1.6-GHz 16x16b asynchronous pipelined multiplier

This paper presents a 16/spl times/16 b fully pipelined multiplier for fine-grain DSP applications. A novel asynchronous handshake protocol is employed to replace the conventional global clock. Based on 0.25 /spl mu/m CMOS technology, HSPICE simulation results indicate that an average data throughput of 1.6 GHz can be achieved at 1.8 V operation.