An efficient behavioral model for delta-sigma modulators

This paper demonstrates an efficient and easily built behavioral model of delta-sigma modulators to fulfil the top-down design procedure for analog circuits. The model can be applied to generate sufficient data as digital input signals for optimizing digital circuits of the decimation stages. The high expandability allows designers to form high-order modulator structures and to add or delete some nonidealities and noise sources in different stages of integrators with consideration of simulation time and accuracy. A 4th-order (MASH 211) delta-sigma modulator is designed with this behavioral model to achieve 320-ksamples/s 14.2-ENOB (effective number of bits) performance.