Design and Evaluation of a Robust Power-Efficient Ternary SRAM Cell

This paper presents a novel ternary Static Random Access Memory (T-SRAM) cell. To validate the functionality of the proposed T-SRAM, carbon nanotube field-effect transistors are selected as a proof-of-concept, whereas either post-CMOS or CMOS technologies can replace it. Our T-SRAM intrinsically eliminates the need to store the intermediate ternary state’s voltage level, thus significantly reducing leakage power and increasing robustness. Extensive SPICE simulation and comparison results show that the proposed T-SRAM can be a promising alternative for CMOS SRAMs deploying in low-power edge AI. Further, the analysis verifies that the proposed design is more robust than previous implementations.