An FPGA-Based Verification Platform for High-Speed Interface IPs

Multiple CMOS ICs for die-2-die (D2D, or chip-2-chip, C2C) integration, typically using 65nm to 7nm processes, are assembled in today's SoC designs. The interconnection between CPU and high-speed interface (I/F) IPs SerDes and memory (DDR or Flash memory), are through HBM, 2.5D and/or SiP following PCIe 4.0 or NVMe protocols. For high-data rate at 100 Gbps (25Gbps $\times 4$ channels) or above communications, D2D is including silicon to photonics (SiPh) ICs, progressing to chiplet technology, to enable heterogeneous CMOS and SiPh integration possible. In either or both of D2D and/or CMOS (si-to-si) to SiPh substrate, data transmissions of the chiplet intra-connection are to be tested, verified and validated. An effective verification FPGA-based platform fit to serve this purpose. This study proposes a customized FPGA platform, for the verification of high-speed I/F IPs, at 100 Gbps and opt to 400 Gbps ($100\ \text{Gbps}\times 4$ channels), its output to a network interface card (NIC, Ethernet 4.0) is tenable to a photonics module via RX/receiver IC and Tx/driver IC of a PAM4-based SerDes. The performance and features of data transferring parameters, such as Bit Error Rate (BER), bandwidth and latency can be measured and validated for proposed applications.