Silicon Phosphorus Process Uniformity Improvement Study in Advanced Node

With CMOS devices continuously scaling down, especially from 14nm and below advanced node, embedded silicon phosphorus (SiP) in source and drain regions has been widely used to improve n-MOSFET device performance through electron mobility enhancement. Normally SiP process use N2 as carrier gas, global wafer uniformity almost can meet device requirement, but this SiP process is easy to form tiny particle, this tiny particle will grows larger with SiGe growth, and finally impact device yield; If we use H2 as carrier gas, SiP film defect quality is better relatively, but SiP film global uniformity is worse than SiP film which use N2 as carrier gas formed. In this paper, we investigated different carrier gas to SiP process effect, including SiP process defect performance and global wafer uniformity performance. According structure lot test result, we found if use N2 as SiP process carrier gas, SiP film uniformity show wafer donut area is thinner than center & edge, but if use H2 as SiP process carrier gas, SiP film uniformity shows the opposite result, that is wafer donut area is thicker than wafer center/edge. Finally, we demonstrated one novel SiP process which combined N2 and H2 carrier gas in one recipe.