Power scaling in nanoscale ballistic MOSFET circuits

The goal of this work was to study power scaling of logic circuits based on nanoscale MOSFETs. For this we have used a simple phenomenological model in which the total power consumption P is the sum of dynamic power aCV/sub DD//sup 2/f and static power proportional to J/sub OFF/V/sub DD/. (Here, a < 1 is the average logic activity factor, C is the total effective load capacitance, and V/sub DD/ is the voltage swing.) The results show that, in contrast to the situation in the drift-diffusion mode, in the ballistic regime both the minimum power per unit channel width and the corresponding optimum V/sub DD/ increase as the channel length decreases. The reason for this different scaling is the fact that in ballistic MOSFETs the current is limited by carrier supply exhaustion rather than scattering inside the channel.