A Low-Power Asynchronous Level Crossing ADC designed in 180nm CMOS process for Electrophysiological Signal Recording Applications

Presented in this paper is the design of a level-crossing ADC for biomedical potentials. This architecture takes advantage of the time sparse nature of neural signal recording applications by only sampling when the signal is moving. A 10-bit architecture with a novel threshold control scheme was chosen to help capture both the higher amplitude local field potentials and lower amplitude action potentials found in these systems. The ADC operates on a power of $13.5 \mu \mathrm{W}$ from a 1.8 V supply and achieves a root-mean-square error (RMSE) of 0.65 mV. The design is implemented and simulated in a 180 nm CMOS process using the Cadence Virtuoso Custom IC design tool.